The present invention relates to a MISFET-mounted semiconductor device and a method for fabricating such a semiconductor device.
With the recent advance in LSI toward higher integration, higher-speed operation, lower voltage application, and the like, reduction in sizes of gate electrodes of metal insulator semiconductor field effect transistors (MISFETs) and interconnections is under progress. Currently, in particular, MISFETs with a gate length as small as about 0.1 to 0.15 μm are just to be put into practical use.
FIGS. 4A through 4E are cross-sectional views illustrating the steps for fabrication of a conventional semiconductor device including MISFETs of a polysilicon gate structure, which is hereinafter referred to as the first prior art. The fabrication process of the semiconductor device of the first prior art will be described with reference to FIGS. 4A through 4E.
In the step shown in FIG. 4A, a silicon oxide film, which is to be gate insulating films, is formed on a silicon substrate 101 as a semiconductor substrate. A polysilicon film, which is to be gate electrodes, is formed on the silicon oxide film. On the polysilicon film, a photoresist film 104 having a desired gate electrode pattern is formed by photolithography. Using the photoresist film as a mask, the polysilicon film and the silicon oxide film are patterned by dry etching, to form gate insulating films 102 and gate electrodes 103. At this stage, the lateral size of the gate electrodes 103 (gate length) is A (for example, 0.15 μm).
In the step shown in FIG. 4B, the photoresist film 104 is removed by ashing with O2 plasma. During the ashing, exposed side faces of the gate electrodes 103 made of polysilicon in n-channel MISFET formation areas are oxidized by a thickness of about 0.005 μm, for example, forming plasma oxide films 105a having a lateral thickness x1 (for example, about 0.01 μm). Although omitted in FIG. 4B, a plasma oxide film is also formed on the silicon substrate 101. In addition, plasma oxide films are also formed on the side faces of gate electrodes in the other areas not shown (p-channel MISFET formation areas, and other transistor formation areas different in the thickness of the gate insulating film).
In the step shown in FIG. 4C, impurity ions are implanted in the silicon substrate 101 using the gate electrodes 103 and the plasma oxide films 105a as a mask, to form n-type LDD layers 106 for the n-channel MISFETs. This ion implantation is performed using arsenic ions under the conditions of an accelerating energy of 10 keV and a dose of 5.0×1014 cm−2, for example. During this ion implantation, the p-channel MISFET formation areas and the like are covered with a photoresist film. This photoresist film must be removed before formation of lightly-doped source/drain regions for p-channel MISFETs and the like.
FIG. 4D illustrates the state of the n-channel MISFET just after completion of ashing for removing the photoresist film covering the p-channel MISFET formation areas and the like. Due to this ashing with O2 plasma, the exposed side faces and top portion of the gate electrode 103 made of polysilicon are further oxidized by a thickness of about 0.005 μm, to form plasma oxide films 105 having a lateral thickness x2 (for example, about 0.02 μm). Although omitted in FIG. 4D, a plasma oxide film is also further formed on the silicon substrate 101.
FIG. 4E illustrates the state of the MISFET after washing with hydrofluoric acid for removal of particles. The plasma oxide films 105 have been removed with the washing with hydrofluoric acid. The resultant gate electrode 103 has a lateral size (gate length) of B (0.13 μm assuming that the polysilicon has been oxidized by a thickness of about 0.01 μm on each side by the twice plasma treatment as described above). That is, the lateral size of the gate electrode is gradually reduced from the original size.
FIGS. 5A through 5E are cross-sectional views illustrating the steps for fabrication of a conventional semiconductor device including MISFETs of a polymetal gate structure, which is hereinafter referred to as the second prior art. The fabrication process of the semiconductor device of the second prior art will be described with reference to FIGS. 5A through 5E.
In the step shown in FIG. 5A, a silicon oxide film, which is to be gate insulating films, is formed on a silicon substrate 101 as a semiconductor substrate. On the silicon oxide film, deposited sequentially are a polysilicon film, a tungsten nitride (WN) film or a titanium nitride (TiN) film as a barrier metal film, and a metal film made of tungsten (W), which are to be gate electrodes. A silicon nitride film is then formed on the resultant substrate by LPCVD. On the silicon nitride film, a photoresist film 107 having a desired gate electrode pattern is formed by photolithography. Using the photoresist film 107 as a mask, the silicon nitride film, the metal film, the barrier metal film, the polysilicon film, and the silicon oxide film are patterned, to form gate insulating films 102, gate electrodes 103 each composed of a bottom gate electrode 103a, a barrier metal film 103b, and a top gate electrode 103c, and gate top insulating films 108.
In the step shown in FIG. 5B, the photoresist film 107 is removed by ashing. Due to the ashing with O2 plasma, exposed side faces of the gate electrodes 103 in the n-channel MISFET formation areas are oxidized, forming plasma oxide films 110. Each plasma oxide film 110 is particularly formed thick on the bottom gate electrode 103a made of polysilicon having a large oxidation rate, hardly formed on the barrier metal film 103b made of WN, and slightly formed on the top gate electrode 103c made of W. Although omitted in FIG. 5B, a plasma oxide film is also formed on the silicon substrate 101. Plasma oxide films are also formed on side faces of gate electrodes in the other areas not shown (p-channel MISFET formation areas, and other transistor formation areas different in the thickness of the gate insulating film).
In the step shown in FIG. 5C, impurity ions are implanted in the silicon substrate 101 using the gate top insulating films 108 and the gate electrodes 103 as a mask, to form n-type LDD layers 106 for the n-channel MISFETs. During this ion implantation, the p-channel MISFET formation areas and the like are covered with a photoresist film. This photoresist film must be removed before formation of p-type LDD layers for the p-channel MISFETs.
FIG. 5C illustrates the state after completion of ashing for removing the photoresist film covering the p-channel MISFET formation areas and the like and subsequent washing with hydrofluoric acid for removal of particles. Since the photoresist film covering the p-channel MISFET formation areas and the like is removed by ashing with O2 plasma as in the removal of the photoresist film 107 shown in FIG. 5B, the side faces of the gate electrodes 103 are further oxidized as in the step shown in FIG. 5B, increasing the thickness of the plasma oxide films 110. That is, each plasma oxide film 110 is formed particularly thick on the bottom gate electrode 103a made of polysilicon having a large oxidation rate, hardly formed on the barrier metal film 103b made of WN, and slightly formed on the top gate electrode 103c made of W.
By the washing with hydrofluoric acid for particle removal, the plasma oxide films 110 are removed, resulting in the contour as shown in FIG. 5C. That is, the side faces of the bottom gate electrodes 103a made of polysilicon have been particularly greatly etched, the side faces of the top gate electrodes 103c made of W have been slightly etched, and the side faces of the gate top insulating films 108 made of silicon nitride have been hardly etched. As a result, the entire gate electrode has a constricted shape.
In the step shown in FIG. 5D, using the gate top insulating films 108 and the gate electrodes 103 as a mask, BF2 ions are implanted in the silicon substrate 101 under the conditions of an accelerated energy of 30 keV and a dose of 5.0×1013 cm−2, for example, to form p-pocket regions 111 for the n-channel MISFETs. Thereafter, a silicon nitride film is deposited on the entire surface of the resultant substrate by LPCVD, and then etched back, to form side walls 112 on the side faces of the gate electrodes 103. The side wall 112 has a recessed contour as a whole following the unevenness of the side faces of the gate electrodes. Using the gate electrodes 103, the gate top insulating films 108, and the side walls 112 as a mask, arsenic ions are implanted in the silicon substrate 101 under the conditions of an accelerating energy of 40 keV and a dose of 4.0×1015 cm−2, for example, to form n-type heavily-doped source/drain layers 113 for the n-channel MISFETs.
In the step shown in FIG. 5E, a boron-phosphosilicate-glass (BPSG) film is deposited on the resultant substrate by atmospheric CVD, and then flattened by annealing for 30 seconds at 900° C. so that the spaces between the gate electrodes are filled with the BPSG film thereby forming an interlayer insulating film 115. During this filling, a void 116 may sometimes be generated somewhere in the interlayer insulating film 115 between the gate electrodes due to the recessed contour of the side walls 112 following the unevenness of the side faces of the gate electrodes.
Thus, the above two conventional semiconductor devices have the following problems. In the MISFET of the polysilicon gate structure as in the first prior art, the lateral size of the gate electrode becomes smaller every time the gate electrode passes through the process steps of removing a photoresist film and washing. This reduction in the lateral size of the gate electrode is not so influential as long as the gate length is sufficiently large. However, with the recent decrease in the gate length to as small as about 0.1 μm, it has turned out that the above reduction in lateral size during the fabrication process causes a problem that is not negligible. As described above, the polysilicon film of the gate electrode is oxidized on both sides by a total thickness of 0.02 μm and the oxidized portions are removed, by the twice removal of the photoresist films with O2 plasma and the subsequent washing and the like. As a result, the gate length of 0.15 μm is reduced to 0.13 μm. If the gate length is 0.1 μm, it is reduced to 0.08 μm. In general, a CMOS device includes transistors of which gate insulating films have two or more different thicknesses. Such transistors different in thickness often require different ion implantation conditions. This necessitates the process step of removing a photoresist film with O2 plasma several times. During the repeated process steps, the growth rate of the plasma oxide film and the rate of wet etching of the oxide film by washing vary depending on the position on the wafer. These variations are exhibited as variations in gate size, and thus the rate of errors from the design size increases. In addition, as shown in FIG. 4E, the overlap amount between the LDD layers 106 and the ends of the gate electrode 103 changes from the initial amount at the time of ion implantation. This causes a problem of increasing the parasitic resistance of the LDD layers and thus reducing the drain current. This problem will not be essentially solved by simply forming the gate electrodes with a largish gate size in expectation of reduction in the lateral size of the gate electrodes.
In the MISFET of the polymetal gate structure or a polycide gate structure as in the second prior art, in addition to the above problems described in the first prior art, the following problem arises. As shown in FIG. 5E, when the gate electrodes and interconnections are of a multilayer structure composed of materials having different etching rates, steps are formed on the exposed side faces of the multilayer structure. Due to the existence of the steps, a void may be formed when the spaces between the gate electrodes and interconnections are filled with an interlayer insulating film in a subsequent step. Such a void tends to move upward during reflowing of the interlayer insulating film to come out of the interlayer insulating film. In some cases, however, a void may fail to come outside, forming a groove on the surface of the interlayer insulating film. In a subsequent step of forming multilayer interconnections, an etching residue may be left in the groove after etching for upper interconnections, and this may possibly cause failure due to a short circuit between interconnections. short circuit between interconnections.